Fusion Compiler features a unique RTL-to-GDSII architecture that enables customers to reimagine what is possible from their designs and take the fast path to achieving maximum differentiation. It delivers superior levels of power, performance and area out-of-the-box, along with industry-best turnaround time.

Formality is an application that uses formal techniques to prove or disprove the functional equivalence of two designs or two cell libraries. For example, you can use Formality to compare a gate-level netlist to its register transfer level (RTL) source or to a modified version of that gate-level netlist. After the comparison, Formality reports whether the two designs or cell libraries are functionally equivalent. The Formality tool can significantly reduce your design cycle by providing an alternative to simulation for regression testing.

SoC level low power signoff can generate design size complexities including 100s of power domains, verification of millions of low power states, and architectural complexities that can arise because of IP integration. Synopsys VC LP seamlessly scales to address the SoCs level of complexity, capacity and performance requirements and enables up to 10X speed up in low power signoff from RTL to PG Netlist.